IGBT Basic (4)

3-2. Latch-up
The IGBT contains a parasitic PNPN thyristor structure between the collector and the emitter. A latch-up means the turning on of the thyristor. When there is action by a thyristor, the IGBT current is no longer controlled by the MOS gate. The IGBT would be destroyed because of excessive power dissipation produced by the amount of current over the rated value between the collector and the emitter.

Causes of latch-up
(1) Static latch-up mode:
Since the conductivity of the drift region under the gate electrode is increased by the introduction of electron current through the channel, most of the holes injected into the drift region are injected at the P body region under the channel and flow to the source metal along the bottom of N+ source. Due to this, the lateral voltage drops across the shunting resistance (RS, refer to Fig. 1) of the P body layer. If this voltage drop becomes greater than the potential barrier of the N+ source / P body layer junction (J3), electrons are injected from the N+ source to the P body layer, and the parasitic NPN transistor (N+ source, P body and N- drift) is turned-on. If the sum of the two NPN, PNP parasitic transistors’ current gain becomes 1 (αNPN + αPNP≥1), latch-up occurs.
(2) Dynamic latch-up mode:
When the IGBT is switched off, the depletion layer of the N- drift / P body junction (J2) is abruptly extended, and the IGBT latches up at a current lower than 1/2 of the static latch-up current due to the displacement current. And because of this, the safe operating area is limited.

Avoidance of latch-up
The first method is to prevent the NPN parasitic transistor from turning on, and the second is to keep the sum of the two NPN, PNP parasitic transistors’ current gain less than 1 (αNPN + αPNP
(1) Application of P+ body This method is applied to most MOS gate power devices. In addition to the body, a highly doped P+ region is formed in the middle of the body, and it covers most of the bottom part of source. When the doping concentration of the P+ region is excessively raised to improve latch-up characteristics, the P+ region affects the threshold voltage by diffusing the channel region and debase the forward characteristics.
(2) Cushion structure p+ Double Implantation: When using a highly doped P+ body, there are limitations in lowering the resistance of the bottom part of N+ source as the doping concentration of the P+ body reduces horizontally due to diffusion. Ion is first injected to form the N+ source. Then high energy p+ ion is injected, and it is put through a thermal process to form P+region at the bottom of the N+ source.
(3) Application of short N+ source: This method reduces the resistance at the bottom of the N+ source.
(4) Reduction of the hole current: The voltage drop across the bottom of the N+ source can be reduced by reducing the hole current passing through the P body. Inserting the highly doped N+ buffer, reducing the space between P bodies, and reducing the current gain by electron irradiation are the methods to reduce the hole current.
(5) Minority Carrier By-Pass: The minority carrier by-pass design has two hole current paths. One is a normal path and the other flows to the emitter contact directly without passing through the bottom of the N+ emitter. So the hole current flowing through the bottom of the N+ emitter is reduced to half, and the latching current density doubles. In spite of an increase in the on-state voltage drop, this method is widely used because it enables safe operation without latch-up phenomenon at higher current and temperature.
(6) Layout: The latch-up characteristics can be improved by changing the N+ source’s cell structure on the surface of the device. Generally, a linearly structured cell has worse forward current conduction characteristics than a cellularly structured cell, but shows better latchup characteristics. A MSS (multiple surface short) structure with better latch-up characteristics as compared to the linear structure has also been developed. There is another method (EBR) used in IGBTs, which increases the voltage drop level across the bottom of N+ source that forward biases the emitter (N+ source region)-base (P body region) junction (J3). This is done by making the voltage drop inside the N+ source by changing the length of the N+ source.
(7) Others: There is also a method to build in a sense IGBT cell and protection devices. This limits the current by reducing the gate voltage automatically, when the current flows over a certain limit. If a large series gate resistance RG is used when the IGBT is applied to a certain set, the turn-off speed is slowed and the diffusion speed of the depletion region of the drift region also slows down. Hence, the dynamic latch-up can be prevented. IGBTs currently under production have the latch-up proof characteristics.
High temperature characteristics (latching current density)
With a rise in temperature, the current gains of the NPN and PNP transistors increase. This decreases the latching current. The effect is aggravated by an increase in the resistance of the P base region due to a decrease in hole mobility.


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